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SMBus/I 2 C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Table 18. Port I/O Registers (I/O Port 5 and 9 Configured as CLA Outputs, Registers
0x05 and 0x09)
REGISTER BIT
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
Don’t care
Port supply
reference
Transition interrupt
enable
Transition detection
bit 1
Transition detection
bit 0
Debounce
Port transition state
Port status
VALUE
x
0
1
0
1
0
0
0
1
0
1
0
1
FUNCTION
Don’t care.
Refers inputs to the VL supply voltage; sets outputs to open drain.
Refers inputs to the V DD supply voltage; sets outputs to push-pull.
Disables the transition interrupt.
Enables the transition interrupt.
Detects the next transition on the port input.
Detects the next transition on the port input.
Disables debouncing of the input port.
Enables debouncing of the input port.
No transition has occurred since the last port read.
A transition has occurred since the last port read.
Port input is logic-low.
Port input is logic-high.
Configurable Logic Array (CLA)
The CLA configures groups of four ports as either a
combinational logic gate up to three inputs, or a two
input exclusive OR/NOR gate (see Tables 12-15).
Eight-port dual groups can be cascaded to form a
two-level gate with the intermediate term brought out
as an output or not, as desired. If fewer than three
gate inputs are needed, the unused CLA input(s)
(which can be any combination of the three CLA
inputs) remain available as independent GPIO ports
(see Figure 8). Use the configurable logic-array enable
register (see Table 16) to enable ports as CLAs. Use the
configurable logic-array lock register (see Table 17) to
permanently lock in any logic-array combination of CLAs
until the next power cycle. Setting D0 and D1 to logic-
high in the configurable logic-array lock register locks the
corresponding bit position in the configurable logic-array
enable register. Additionally, the appropriate CLA_ regis-
ter (addresses 0x28 and 0x29) cannot be changed.
The configurable logic-array lock register is unlocked
on power-up, or by RST when configured by the
RSTPOR bit in the configure register. Each lock bit can
only be written to once per power cycle.
A CLA’s input(s) and output can be read through the
serial interface like a normal input port. The MAX7302
creates a gate that provides an independent real-time
logic function, and every node of it can be examined
through the I 2 C interface with optional debounce and
transition detection.
Setting bits D0 and D1 to logic-high enables the CLA
functionality and sets ports P5 and P9 as CLA outputs
(see Table 16). When in CLA mode, the port I/O regis-
ter data is interpreted differently for CLA output ports
(see Table 18). Bit D7 that normally selects the port
direction is ignored because either port P5 or P9 is
always an output. Bit D6 sets both the CLA output type
(push-pull or open drain) and the logic threshold for
reading the CLA output status back through the I 2 C
interface. The other bits set the readback options, such
as debounce and transition detection interrupt.
20
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